Tarea Digitales
Enviado por Vicente Marin Marti • 29 de Agosto de 2022 • Tarea • 663 Palabras (3 Páginas) • 66 Visitas
Tabla de Verdad maquina QuienGana.
[pic 1]
Ejemplo de Comparador.
En el caso de este trabajo no utilicé la parte de A=B ya que se representa con un A>B = 0 y A<B = 0.[pic 2]
CODIGO VERILOG
module controlA (input logic clk,
input logic reset,
input logic [1:0] DA,
input logic BA,
output logic FA
output puntajeA[2:0])
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5, S6} statetype;
statetype stateA, nextstateA;
always_ff @ (posedge clk, posedge reset)
if (reset) stateA <= S0;
else stateA <= nextstateA;
always_comb
case (stateA)
S0: if (BA | ~DA[1] & ~DA[0]) nextstateA = S0;
else if (~BA & ~DA[1] & DA[0]) nextstateA = S2;
else nextstateA = S3;
S2: if (BA | ~DA[1] & ~DA[0]) nextstateA = S2;
else if (~BA & ~DA[1] & DA[0]) nextstateA = S4;
else nextstateA = S5;
S3: if (BA | ~DA[1] & ~DA[0]) nextstateA = S3;
else if (~BA & ~DA[1] & DA[0]) nextstateA = S5;
else nextstateA = S6;
S4: nextstateA = S4;
S5: nextstateA = S5;
S6: nextstateA = S6;
default: nextstateA = S0;
assign puntajeA=nextstateA
endcase
assign FA = (stateA == S6);
endmodule
module controlB (input logic clk,
input logic reset,
input logic [1:0] DB,
input logic BB,
output logic FB,
output puntajeB[2:0])
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5, S6} statetype;
statetype stateB, nextstateB;
always_ff @ (posedge clk, posedge reset)
if (reset) stateB <= S0;
else stateB <= nextstateB;
always_comb
case (stateB)
S0: if (BB | ~DB[1] & ~DB[0]) nextstateB = S0;
else if (~BB & ~DB[1] & DB[0]) nextstateB = S2;
else nextstateB = S3;
S2: if (BB | ~DB[1] & ~DB[0]) nextstateB = S2;
else if (~BB & ~DB[1] & DB[0]) nextstateB = S4;
else nextstateB = S5;
S3: if (BB | ~DB[1] & ~DB[0]) nextstateB = S3;
else if (~BB & ~DB[1] & DB[0]) nextstateB = S5;
else nextstateB = S6;
S4: nextstateB = S4;
S5: nextstateB = S5;
S6: nextstateB = S6;
default: nextstateB = S0;
assign puntajeB=nextstateB
endcase
assign FB = (stateB == S6);
endmodule
Module comparador (input logic [2:0] Qa,
input logic [2:0] Qb,
...