Tarea Electronica

[pic 1][pic 2]

INSTITUTO POLITECNICO NACIONAL

ESCUELA SUPERIOR DE INGENIERIA

MECANICA Y ELECTRICA

____________________________________________

ELECTRÓNICA

____________________________________________

CORREA ARGUMOSA JORGE EDUARDO

HARO CAMPOS LUIS FERNANDO

MARTINEZ ORTEGA PEDRO DAVID

21/ENE/2021

5RM3

CARPETA 1

`include "Addition-Subtraction.v"

`define N_TESTS 100000

module Addition_tb;

reg clk = 0;

reg [31:0] a_operand;

reg [31:0] b_operand;

wire [31:0] result;

reg AddBar_Sub;

reg [31:0] Expected_result;

reg [95:0] testVector [`N_TESTS-1:0];

reg test_stop_enable;

integer mcd;

integer test_n = 0;

integer pass   = 0;

integer error  = 0;

Addition_Subtraction DUT(a_operand,b_operand,AddBar_Sub,Exception,result);

always #5 clk = ~clk;

initial  

AddBar_Sub = 1'b0;

begin

        $readmemh("TestVectorAddition", testVector);

        mcd = $fopen("ResultsAdd.txt");

end

always @(posedge clk)

begin

        {a_operand,b_operand,Expected_result} = testVector[test_n];

        test_n = test_n + 1'b1;

        #2;

        if (result[31:11] == Expected_result[31:11])

        begin

        pass = pass + 1'b1;

        end

        if (result[31:11] != Expected_result[31:11])

        begin

        $fdisplay (mcd,"Test Failed Expected Result = %h, Obtained result = %h, Test Number -> %d",Expected_result,result,test_n);

        error = error + 1'b1;

        end

        if (test_n >= `N_TESTS)

        begin

        $fdisplay(mcd,"Completed %d tests, %d passed and %d fails.", test_n, pass, error);

        test_stop_enable = 1'b1;

        end

end

always @(posedge test_stop_enable)

begin

$fclose(mcd);

$finish;

end

endmodule

[pic 3]

`include "Addition.v"

module Addition_tb;

reg [31:0] a_operand,b_operand;

reg clk=1'b0,

        reset=1'b1;

reg AddBar_Sub;

wire [31:0] result;

wire Exception;

Addition_Subtraction dut(a_operand,b_operand,AddBar_Sub,Exception,result);

always #5 clk = ~clk;

initial

begin

AddBar_Sub = 1'b0;

iteration (32'h4201_51EC,32'h4242_147B,32'h42A1_B333,`__LINE__);

iteration (32'h4068_51EC,32'h4090_A3D7,32'h4102_6666,`__LINE__);

iteration (32'h4195_0A3D,32'h419B_47AE,32'h4218_28F6,`__LINE__);

iteration (32'h4217_999A,32'h3F8C_CCCD,32'h421C_0000,`__LINE__);

iteration (32'h4383_C7AE,32'h4164_F5C3,32'h438A_EF5C,`__LINE__);

iteration (32'h4542_77D7,32'h453B_8FD7,32'h45BF_03D7,`__LINE__);

iteration (32'h3F3A_E148,32'h3EB33333,32'h3F8A_3D71,`__LINE__);

iteration (32'h3F7D_70A4,32'h3F7D_70A4,32'h3FFD_70A4,`__LINE__);

iteration (32'h3F40_0000,32'h3E94_7AE1,32'h3F85_1EB8,`__LINE__);

iteration (32'h4B7F_FFFF,32'h3F80_0000,32'h4B80_0000,`__LINE__);

iteration (32'h4B7F_FFFF,32'h4000_0000,32'h4B80_0001,`__LINE__);

iteration (32'h4B7F_FFFF,32'h4B7F_FFFF,32'h4BFF_FFFF,`__LINE__);

iteration (32'h4B7F_FFFE,32'h3F80_0000,32'h4B7F_FFFF,`__LINE__);

iteration (32'hBF3A_E148,32'h3EC7_AE14,32'hBEAE_147B,`__LINE__);

iteration (32'hC207_C28F,32'h4243_B852,32'h416F_D70A,`__LINE__);

iteration (32'hBDB2_2D0E,32'h4305_970A,32'h4305_80C5,`__LINE__);

iteration (32'h4E6B_79A3,32'hCCEB_79A3,32'h4E4E_0A6F,`__LINE__);

iteration (32'h4B80_0000,32'hCB80_0000,32'h0000_0000,`__LINE__);

iteration (32'h4B7F_FFFF,32'hCB7F_FFFF,32'h0000_0000,`__LINE__);

AddBar_Sub = 1'b1;

iteration (32'h40A00000,32'h40C00000,32'hBF800000,`__LINE__);

iteration (32'h40C00000,32'h40A00000,32'h3F800000,`__LINE__);

iteration (32'hC0C00000,32'hC0A00000,32'hBF800000,`__LINE__);

iteration (32'hC0A00000,32'hC0C00000,32'h3F800000,`__LINE__);

iteration (32'h40C00000,32'hC0A00000,32'h41300000,`__LINE__);

iteration (32'h40A00000,32'hC0C00000,32'h41300000,`__LINE__);

iteration (32'hC0A00000,32'h40C00000,32'hC1300000,`__LINE__);

...