Ejercicio en HDL

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DEPARTAMENTO DE ELÉCTRICA Y ELECTRÓNICA

CARRERA DE TELECOMUNICACIONES

Asignatura: Circuitos y Sistemas Digitales

INFORME EJERCICIO VHDL

Tema: Ejercicio en HDL

Nombre: Leslie Titoaña

NRC: 7365

Docente: Ing. Pablo Francisco Ramos Vargas

Quito - Ecuador

Tema: VHDL

Objetivo: Desarrollar ejercicios VHDL mediante la aplicación del software Active y comprender asi el comportamiento del ejercicio el cual se basa en el alarma de un vehículo.

Desarrollo

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity testbuzzer is

-- Port ( );

end testbuzzer;

architecture testbuzzer of testbuzzer is

signal s1,s2,s3,s4 : std_logic; -- in/outssignal s1,s2,s3 : std_logic; -- in/outs

component Buzzer

 port(

DOOR : in STD_LOGIC;

IGNITION : in STD_LOGIC;

SBELT : in STD_LOGIC;

WARNING : out STD_LOGIC

 );

end component Buzzer;

begin --comportamiento

operation:Buzzer

port map(DOOR=>s1,IGNITION=>s2,SBELT=>s3, WARNING=>s4); --Maps ports from component to test bench

-- purpose: simulation

-- type : combinational

-- inputs : 789

-- outputs: s1,s2,s3

stimulus: process

begin -- process stimulus

s1<='0';s2<='0';s3<='0'; wait for 20 ns; -- Keeps s1 and s2 at 0 for 20 nano seconds

s1<='0';s2<='0';s3<='1'; wait for 20 ns;

s1<='0';s2<='1';s3<='0'; wait for 20 ns; -- Keeps s1at 0 and s2 at 1 for 20 nano seconds

s1<='0';s2<='1';s3<='1'; wait for 20 ns; -- Keeps s1 at 1 and s2 at 0 for 20 nano seconds

s1<='1';s2<='0';s3<='0'; wait for 20 ns;-- Keeps s1 and s2 at 0 for 20 nano seconds

s1<='1';s2<='0';s3<='1'; wait for 20 ns;

s1<='1';s2<='1';s3<='0'; wait for 20 ns;

...